AG256 CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 256 Logic Elements with LQFP-100 package.

•  Low-Cost and low-power CPLD
•  Instant-on, non-volatile standard compatible architecture.
•  Up to 4 global clock lines in the global clock network that drive throughout the entire device.
•  Provides programmable fast propagation delay and clock-to-output times.
•  UFM supports non-volatile storage up to 256 Kbits.
•  Supports 3.3-V logic level
•  Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
•  Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
•  ISP circuitry compliant with IEEE Std. 1532
•  3.3-V LVCMOS and LVTTL standards
•  Emulated LVDS output (LVDS_E_3R)
•  Emulated RSDS output (RSDS_E_3R)

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