A Digital Oscilloscope Solution Using AG32 to Replace GD407

There are multiple digital mini oscilloscopes on the market, which are particularly small and convenient to carry. Single channel, labeled with a bandwidth of 100Mhz, and a sampling rate of 500MS. This high sampling rate requires the use of high-speed AD and high-performance processors. The original plan used AD9288 dual channel 8bit 100Mhz high-speed AD, and GD32F407 with a maximum operating frequency of 168MHz.

AG32VF407 is the most high-end model in the AG32 series, which is pin compatible with GD407, but has unique characteristics.So AG32 can replace GD407 in this solution perfectly.
Internal block diagram of AG32 series heterogeneous chips:

1、 Ultra high cost-effectiveness (ultra high main frequency gives developers more time for data processing and analysis)
RISC-V open-source kernel, with an ultra-high main frequency of 248 MHz, is unmatched by STM32F207/407. In addition, there is also a 2K FPGA, which is equivalent to the capacity of four Altera CPLD EPM570 chips, which is equivalent to one ST207 and four EPM570 AGM32 chips with extremely high cost-effectiveness.
2、 Flexible custom interface: (Implementation of high-speed AD data interface)
The high-speed AD9288 data interface used in digital oscilloscopes can be achieved through the FPGA in AG32. This clock has a speed of up to 100 MHz, and ordinary MCU does not have an interface similar to this synchronization mechanism to read data.
3、 Customized hardware acceleration module (to achieve the triggering function of the oscilloscope)
When the trigger of the oscilloscope requires the voltage to be lower or higher than the set voltage, the subsequent waveform sampling begins. This voltage comparison can be handed over to FPGA for implementation.
4、 FPGA/MCU coordinate with each other to maximize performance
FPGA is best at parallel acquisition, analysis, and processing of large amounts of data. This 125M (overclocking) high-speed AD data sampling, even if DMA data reading is used, will frequently preempt the AHB bus with the MCU, resulting in extremely low operating efficiency of the MCU. If FPGA were used for caching, it would be much better, as it would significantly reduce the preemption of the AHB bus. Give MCU more time to refresh the waveform display and perform some human-machine interface operations. FPGA can also scale and filter the collected data, helping MCU complete data processing before waveform display as much as possible.
5、 Digital interface redirection (easy to complete with 2-layer PCB for any application)
PIN defined by AG32 series_ XX can be defined as any digital interface using software, such as UART, SPI, IIC, PWM, IO, etc. Except for the simulation part, ADC, DAC, CMP, and USB, all other interfaces can be defined arbitrarily. By adjusting the order of the digital interface section according to the PCB layout, the 2-layer board can be easily completed. The board laid out in this way not only looks elegant, but also has more reliable performance, and there is basically no cross wiring situation.
6、 Port driver capability can be defined arbitrarily
As needed, the driver capability of each port can be defined arbitrarily, greatly enhancing the anti-interference ability of the interface
7、 Anti cracking function
Many products erase the MARK number of the main control chip before sale to prevent competitors from plagiarizing. However, friends can guess and verify which model of the main control chip this is based on peripheral circuits such as SPI flash, IIC eeprom, UART port, and other corresponding pins. But if you use AGM's MCU, you will find that you have no way of knowing.